View EDD2516AMTA-6B-E_4503058.PDF datasheet online --- IC-ON-LINE

Datasheet File OCR Text:

DATA SHEET
256M bits DDR SDRAM
EDD2516AMTA-6B-E (16M words x 16 bits)
Description
The EDD2516AMTA is 256M bits Double Data Rate (DDR) SDRAM organized as 4,194,304 words x 16 bits x 4 banks. Read and write operations are performed at the cross points of the CK and the /CK. This highspeed data transfer is realized by the 2 bits prefetchpipelined architecture. Data strobe (DQS) both for read and write are available for high speed and reliable data bus design. By setting extended mode resister, the on-chip Delay Locked Loop (DLL) can be set enable or disable. They are packaged in standard 66pin plastic TSOP (II).
Pin Configurations
/xxx indicates active low signal.
66-pin Plastic TSOP(II)
VDD DQ0 VDDQ DQ1 DQ2 VSSQ DQ3 DQ4 VDDQ DQ5 DQ6 VSSQ DQ7 NC VDDQ LDQS NC VDD NC LDM /WE /CAS /RAS /CS NC BA0 BA1 A10(AP) A0 A1 A2 A3 VDD 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 33 66 65 64 63 62 61 60 59 58 57 56 55 54 53 52 51 50 49 48 47 46 45 44 43 42 41 40 39 38 37 36 35 34 VSS DQ15 VSSQ DQ14 DQ13 VDDQ DQ12 DQ11 VSSQ DQ10 DQ9 VDDQ DQ8 NC VSSQ UDQS NC VREF VSS UDM /CK CK CKE NC A12 A11 A9 A8 A7 A6 A5 A4 VSS
EO
Features
* 2.5 V power supply: VDD, VDDQ = 2.5V 0.2V * Data rate: 333Mbps (max.) * Double Data Rate architecture; two data transfers per clock cycle * Bi-directional data strobe (DQS) is transmitted /received with data for capturing data at the receiver * Data inputs, outputs, and DM are synchronized with DQS * 4 internal banks for concurrent operation * DQS is edge aligned with data for READs; center aligned with data for WRITEs * Differential clock inputs (CK and /CK) * DLL aligns DQ and DQS transitions with CK transitions * Commands entered on each positive CK edge; data and data mask referenced to both edges of DQS * Data mask (DM) for write data * Auto precharge option for each burst access * SSTL_2 compatible I/O * Programmable burst length (BL): 2, 4, 8 * Programmable /CAS latency (CL): 2, 2.5 * Programmable output driver strength: normal/weak * Refresh cycles: 8192 refresh cycles/64ms 7.8s maximum average periodic refresh interval * 2 variations of refresh Auto refresh Self refresh * TSOP (II) package with lead free solder (Sn-Bi) RoHS compliant
Document No. E0749E10 (Ver. 1.0) Date Published June 2005 (K) Japan Printed in Japan URL: http://www.elpida.com
L
Pr
This product became EOL in March, 2007.
(c)Elpida Memory, Inc. 2005
od
A0 to A12 BA0, BA1
DQ0 to DQ15
(Top view)
UDQS/LDQS /CS /RAS /CAS /WE UDM/LDM CK /CK CKE VREF VDD VSS VDDQ VSSQ NC
Address input Bank select address Data-input/output Input and output data strobe Chip select Row address strobe command Column address strobe command Write enable Input mask Clock input Differential clock input Clock enable Input reference voltage Power for internal circuit Ground for internal circuit Power for DQ circuit Ground for DQ circuit No connection
t uc
EDD2516AMTA-6B-E
Ordering Information
Part number EDD2516AMTA-6B-E Mask version M Organization (words x bits) 16M x 16 Internal banks Data rate Mbps (max.) 333 Speed bin (CL-tRCD-tRP) DDR-333B (2.5-3-3) Package 66-pin Plastic TSOP (II)
Part Number
E D D 25 16 A M TA - 6B - E
Elpida Memory Type D: Monolithic Device
EO
Product Family D: DDR SDRAM Density / Bank 25: 256M / 4-bank Organization 16: x16 Power Supply, Interface A: 2.5V, SSTL_2
Environment Code E: Lead Free
Speed 6B: DDR333B (2.5-3-3) Package TA: TSOP (II) Die Rev.
Data Sheet E0749E10 (Ver. 1.0)
L Pr od t uc
2
EDD2516AMTA-6B-E
CONTENTS Description .................................................................................................................................................... 1 Features ........................................................................................................................................................ 1 Pin Configurations......................................................................................................................................... 1 Ordering Information ..................................................................................................................................... 2 Part Number.................................................................................................................................................. 2 Electrical Specifications ................................................................................................................................ 4 Block Diagram............................................................................................................................................. 11 Pin Function ................................................................................................................................................ 12 Command Operation................................................................................................................................... 14 Simplified State Diagram ............................................................................................................................ 21 Operation of the DDR SDRAM ................................................................................................................... 22 Timing Waveforms ...................................................................................................................................... 24 Package Drawing........................................................................................................................................ 30 Recommended Soldering Conditions ......................................................................................................... 31
EO
Data Sheet E0749E10 (Ver. 1.0)
L Pr od t uc
3
EDD2516AMTA-6B-E
Electrical Specifications
* All voltages are referenced to VSS (GND). * After power up, wait more than 200 s and then, execute power on sequence and CBR (Auto) refresh before proper device operation is achieved. Absolute Maximum Ratings
Parameter Voltage on input pin relative to VSS Voltage on DQ and DQS pin relative to VSS Supply voltage relative to VSS Supply voltage for output relative to VSS Short circuit output current Power dissipation Symbol VI VIO VDD VDDQ IOS PD TA Tstg Rating -0.5 to VDD +0.5 -0.5 to VDDQ +0.5 -0.5 to +3.7 -0.5 to +3.7 50 1.0 0 to +70 -55 to +125 Unit V V V V mA W C C Note
EO
Operating temperature Storage temperature Parameter Supply voltage Input reference voltage Termination voltage Input high voltage Input low voltage Input voltage level, CK and /CK inputs Input differential cross point voltage, CK and /CK inputs Input differential voltage, CK and /CK inputs
Caution Exposing the device to stress above those listed in Absolute Maximum Ratings could cause permanent damage. The device is not meant to be operated under conditions outside the limits described in the operational section of this specification. Exposure to Absolute Maximum Rating conditions for extended periods may affect device reliability. Recommended DC Operating Conditions (TA = 0C to 70C)
Symbol VDD, VDDQ VSS, VSSQ VREF VTT min. 2.3 0 typ. 2.5 0 max. 2.7 0 0.51 x VDDQ VREF + 0.04 VDDQ + 0.3 VREF - 0.15 VDDQ + 0.3 Unit V V V V V V V 2 Notes 1
L
VIH (DC) VIL (DC) VIN (DC) VIX (DC) VID (DC)
Pr
0.49 x VDDQ VREF - 0.04 VREF + 0.15 -0.3 -- -- -0.3 -- 0.5 x VDDQ - 0.2V 0.36 --
0.50 x VDDQ
VREF
od
0.5 x VDDQ
0.5 x VDDQ + 0.2V V VDDQ + 0.6 V 3, 4
Notes: 1. 2. 3. 4.
VDDQ must be lower than or equal to VDD. VIN (DC) specifies the allowable DC execution of each differential input. VID (DC) specifies the input differential voltage required for switching. VIH (CK) min assumed over VREF + 0.18V, VIL (CK) max assumed under VREF - 0.18V if measurement.
t uc
Data Sheet E0749E10 (Ver. 1.0)
4
EDD2516AMTA-6B-E
AC Overshoot/Undershoot Specification
Parameter Maximum peak amplitude allowed for overshoot Maximum peak amplitude allowed for undershoot The area between the overshoot signal and VDD must be less than or equal to The area between the undershoot signal and GND must be less than or equal to Specification 1.6V 1.6V 4.5V-ns 4.5V-ns
5 4 3 2 Volts (V) 1 0 -1 -2 -3 0 1 2 3 Time (ns)
Maximum amplitude = 1.6V Overshoot area 4.5V-ns (max.)
VDD Ground
Undershoot area 4.5V-ns (max.)
EO
Data Sheet E0749E10 (Ver. 1.0)
4
5
6
L Pr od t uc
5
EDD2516AMTA-6B-E
DC Characteristics 1 (TA = 0C to +70C, VDD, VDDQ = 2.5V 0.2V, VSS, VSSQ = 0V)
Parameter Operating current (ACT-PRE) Operating current (ACT-READ-PRE) Idle power down standby current Floating idle standby current Quiet idle standby current Active power down standby current Symbol IDD0 IDD1 IDD2P IDD2F IDD2Q IDD3P IDD3N IDD4R IDD4W IDD5 IDD6 IDD7A Grade max. 85 125 4 35 35 25 45 250 200 145 3 330 Unit mA mA mA mA mA mA mA mA mA mA mA mA Test condition CKE VIH, tRC = tRC (min.) CKE VIH, BL = 4, CL = 2.5, tRC = tRC (min.) CKE VIL CKE VIH, /CS VIH DQ, DQS, DM = VREF CKE VIH, /CS VIH DQ, DQS, DM = VREF CKE VIL CKE VIH, /CS VIH tRAS = tRAS (max.) CKE VIH, BL = 2, CL = 2.5 CKE VIH, BL = 2, CL = 2.5 tRFC = tRFC (min.), Input VIL or VIH Input VDD - 0.2 V Input 0.2 V BL = 4 Notes 1, 2, 9 1, 2, 5 4 4, 5 4, 10 3 3, 5, 6 1, 2, 5, 6 1, 2, 5, 6
EO
Active standby current Operating current (Burst read operation) Operating current (Burst write operation) Auto Refresh current Self refresh current Operating current (4 banks interleaving) Parameter Input leakage current Output leakage current Output high current Output low current Symbol ILI ILO IOH IOL
Data Sheet E0749E10 (Ver. 1.0)
1, 5, 6, 7
Notes: 1. These IDD data are measured under condition that DQ pins are not connected. 2. One bank operation. 3. One bank active. 4. All banks idle. 5. Command/Address transition once per one clock cycle. 6. DQ, DM and DQS transition twice per one clock cycle. 7. 4 banks active. Only one bank is running at tRC = tRC (min.) 8. The IDD data on this table are measured with regard to tCK = tCK (min.) in general. 9. Command/Address transition once every two clock cycle. 10. Command/Address stable at VIH or VIL. DC Characteristics 2 (TA = 0C to +70C, VDD, VDDQ = 2.5V 0.2V, VSS, VSSQ = 0V)
min. -2 -5 -16.2 16.2 max. 2 Unit
L
Pr
A 5 A -- mA -- mA
od
6
Test condition
Notes
VDD VIN VSS VDDQ VOUT VSS VOUT = 1.95V VOUT = 0.35V
t uc
EDD2516AMTA-6B-E
Pin Capacitance (TA = +25C, VDD, VDDQ = 2.5V 0.2V)
Parameter Input capacitance Symbol CI1 CI2 Delta input capacitance Cdi1 Cdi2 Data input/output capacitance Delta input/output capacitance CI/O Cdio Pins CK, /CK All other input pins CK, /CK All other input-only pins DQ, DM, DQS DQ, DM, DQS min. 2.0 2.0 -- -- 4.0 -- typ. -- -- -- -- -- -- max. 3.0 3.0 0.25 0.5 5 0.5 Unit pF pF pF pF pF pF Notes 1 1 1 1 1, 2, 1
Notes: 1. These parameters are measured on conditions: TA = +25C. 2. DOUT circuits are disabled.
f = 100MHz, VOUT = VDDQ/2, VOUT = 0.2V,
EO
Parameter Clock cycle time (CL = 2) (CL = 2.5) CK high-level width CK low-level width CK half period DQ output access time from CK, /CK DQS to DQ skew Data hold skew factor Read preamble Read postamble DQ and DM input setup time DQ and DM input hold time Write preamble setup time Write preamble Write postamble DQS input high pulse width DQS input low pulse width
Data Sheet E0749E10 (Ver. 1.0)
AC Characteristics (TA = 0C to +70C, VDD, VDDQ = 2.5V 0.2V, VSS, VSSQ = 0V)
-6B Symbol tCK tCK tCH tCL tHP tAC tDQSCK tDQSQ min. 7.5 6 0.45 0.45 min (tCH, tCL) -0.7 -0.6 -- max. 12 12 0.55 0.55 -- 0.7 0.6 0.45 -- 1 0.7 0.7 1.1 Unit ns ns tCK tCK tCK ns ns ns ns ns ns ns tCK tCK ns ns ns ns tCK tCK 9 8 8 7 5, 11 6, 11 2, 11 2, 11 3 Notes 10
DQS output access time from CK, /CK
DQ/DQS output hold time from DQS
Data-out high-impedance time from CK, /CK tHZ Data-out low-impedance time from CK, /CK tLZ
DQ and DM input pulse width
Write command to first DQS latching transition DQS falling edge to CK setup time DQS falling edge hold time from CK
Address and control input setup time Address and control input hold time Address and control input pulse width
L
Pr
tQH tHP - tQHS -- tQHS -0.7 -0.7 0.9 tRPRE tRPST tDS tDH tDIPW tWPRES tWPRE tWPST tDQSS tDSS tDSH tDQSH tDQSL tIS tIH tIPW 0.3 0.50 0.50 1.75 0 0.25 0.4 0.75 0.2 0.2 0.35 0.35 0.75 0.75 2.2
od
0.7 -- -- -- -- -- 0.6 1.25 -- -- -- -- -- -- --
t uc
tCK tCK tCK tCK tCK ns 8 ns 8 ns 7
7
EDD2516AMTA-6B-E
-6B Parameter Mode register set command cycle time Active to Precharge command period Symbol tMRD tRAS min. 2 42 60 72 18 18 tRCD min. 12 15 max. -- 120000 -- -- -- -- -- -- -- Unit tCK ns ns ns ns ns ns ns ns tCK tCK s 13 Notes
Active to Active/Auto refresh command tRC period Auto refresh to Active/Auto refresh command tRFC period Active to Read/Write delay Precharge to active command period Active to Autoprecharge delay Active to active command period Write recovery time tRCD tRP tRAP tRRD tWR
EO
Data Sheet E0749E10 (Ver. 1.0)
Auto precharge write recovery and precharge tDAL time Internal write to Read command delay Average periodic refresh interval tWTR tREF
(tWR/tCK) + (tRP/tCK) -- 1 -- -- 7.8
Notes: 1. On all AC measurements, we assume the test conditions shown in the next page. For timing parameter definitions, see `Timing Waveforms' section. 2. This parameter defines the signal transition delay from the cross point of CK and /CK. The signal transition is defined to occur when the signal level crossing VTT. 3. The timing reference level is VTT. 4. Output valid window is defined to be the period between two successive transition of data out or DQS (read) signals. The signal transition is defined to occur when the signal level crossing VTT. 5. tHZ is defined as DOUT transition delay from Low-Z to High-Z at the end of read burst operation. The timing reference is cross point of CK and /CK. This parameter is not referred to a specific DOUT voltage level, but specify when the device output stops driving. 6. tLZ is defined as DOUT transition delay from High-Z to Low-Z at the beginning of read operation. This parameter is not referred to a specific DOUT voltage level, but specify when the device output begins driving. 7. Input valid windows is defined to be the period between two successive transition of data input or DQS (write) signals. The signal transition is defined to occur when the signal level crossing VREF. 8. The timing reference level is VREF. 9. The transition from Low-Z to High-Z is defined to occur when the device output stops driving. A specific reference voltage to judge this transition is not given. 10. tCK (max.) is determined by the lock range of the DLL. Beyond this lock range, the DLL operation is not assured. 11. tCK = tCK (min) when these parameters are measured. Otherwise, absolute minimum values of these values are 10% of tCK. 12. VDD is assumed to be 2.5V 0.2V. VDD power supply variation per cycle expected to be less than 0.4V/400 cycle. 13. tDAL = (tWR/tCK)+(tRP/tCK) For each of the terms above, if not already an integer, round to the next highest integer. Example: For -6B Speed at CL = 2.5, tCK = 6ns, tWR = 15ns and tRP= 18ns, tDAL = (15ns/6ns) + (18ns/6ns) = (3) + (3) tDAL = 6 clocks
L
Pr
8
od
t uc
EDD2516AMTA-6B-E
Test Conditions
Parameter Input reference voltage Termination voltage Input high voltage Input low voltage Input differential voltage, CK and /CK inputs Input differential cross point voltage, CK and /CK inputs Input signal slew rate Symbol VREF VTT VIH (AC) VIL (AC) VID (AC) VIX (AC) SLEW Value VDDQ/2 VREF VREF + 0.80 VREF - 0.80 1.6 VREF 1 Unit V V V V V V V/ns
EO
Data Sheet E0749E10 (Ver. 1.0)
tCK CK VID /CK tCL tCH VIX VDD VIH VIL VREF VSS
VDD VREF VSS
L
DQ
t
SLEW = (VIH (AC) - VIL (AC))/t
Pr
VTT Measurement point RT = 50
Input Waveforms and Output Load
od
CL = 30pF
t uc
9
EDD2516AMTA-6B-E
Timing Parameter Measured in Clock Cycle
Number of clock cycle tCK Parameter Write to pre-charge command delay (same bank) Read to pre-charge command delay (same bank) Write to read command delay (to input all data) Burst stop command to write command delay (CL = 2) (CL = 2.5) Burst stop command to DQ High-Z (CL = 2) Symbol tWPD tRPD tWRD tBSTW tBSTW tBSTZ tBSTZ tRWD tRWD tHZP tHZP tWCD tWR tDMD tMRD tSNR tSRD 6ns min. 4 + BL/2 BL/2 2 + BL/2 2 3 2 2.5 2 + BL/2 3 + BL/2 2 2.5 1 3 0 2 12 200 max. -- -- -- -- -- 2 2.5 -- -- 2 2.5 1 -- 0 -- -- -- 1 -- Unit tCK tCK tCK tCK tCK tCK tCK tCK tCK tCK tCK tCK tCK tCK tCK tCK tCK tCK tCK
EO
(CL = 2.5) (CL = 2.5) (CL = 2.5) Write recovery DM to data in latency Power down entry
Data Sheet E0749E10 (Ver. 1.0)
Read command to write command delay (to output all data) (CL = 2) Pre-charge command to High-Z (CL = 2) Write command to data in latency
Mode register set command cycle time Self refresh exit to non-read command Self refresh exit to read command
Power down exit to command input
L
Pr
tPDEN 1 tPDEX 1
od t uc
10
EDD2516AMTA-6B-E
Block Diagram
CK /CK CKE
Clock generator
Bank 3 Bank 2 Bank 1
A0 to A12, BA0, BA1
Mode register
Row address buffer and refresh counter
Row decoder
Memory cell array Bank 0
Command decoder
/CS /RAS /CAS /WE
Control logic
EO
Data Sheet E0749E10 (Ver. 1.0)
Sense amp. Column address buffer and burst counter Column decoder
L
Data control circuit
Latch circuit
DQS
Pr
CK, /CK DLL
Input & Output buffer
DM
DQ
od t uc
11
EDD2516AMTA-6B-E
Pin Function
CK, /CK (input pins) The CK and the /CK are the master clock inputs. All inputs except DM, DQS and DQs are referred to the cross point of the CK rising edge and the /CK falling edge. When a read operation, DQS and DQs are referred to the cross point of the CK and the /CK. When a write operation, DQS and DQs are referred to the cross point of the DQS and the VREF level. DQS for write operation is referred to the cross point of the CK and the /CK. CK is the master clock input to this pin. The other input signals are referred at CK rising edge. /CS (input pin) When /CS is Low, commands and data can be input. When /CS is High, all inputs are ignored. However, internal operations (bank active, burst operations, etc.) are held. /RAS, /CAS, and /WE (input pins) These pins define operating commands (read, write, etc.) depending on the combinations of their voltage levels. See "Command operation". A0 to A12 (input pins) Row address (AX0 to AX12) is determined by the A0 to the A12 level at the cross point of the CK rising edge and the /CK falling edge in a bank active command cycle. Column address (See "Address Pins Table") is loaded via the A0 to the A8 at the cross point of the CK rising edge and the /CK falling edge in a read or a write command cycle. This column address becomes the starting address of a burst operation. [Address Pins Table]
Part number EDD2516AMTA
EO
Bank 0 Bank 1 Bank 2 Bank 3
Data Sheet E0749E10 (Ver. 1.0)
A10 (AP) (input pin) A10 defines the precharge mode when a precharge command, a read command or a write command is issued. If A10 = High when a precharge command is issued, all banks are precharged. If A10 = Low when a precharge command is issued, only the bank that is selected by BA1/BA0 is precharged. If A10 = High when read or write command, auto-precharge function is enabled. While A10 = Low, auto-precharge function is disabled. BA0 and BA1 (input pins) BA0, BA1 are bank select signals (BA). The memory array is divided into bank 0, bank 1, bank 2 and bank 3. (See Bank Select Signal Table)
[Bank Select Signal Table]
BA0 L H L H
Remark: H: VIH. L: VIL.
L
Address (A0 to A12) Column address AY0 to AY8
Row address AX0 to AX12
Pr
12
od
BA1 L L H H
t uc
EDD2516AMTA-6B-E
CKE (input pin) This pin determines whether or not the next CK is valid. If CKE is High, the next CK rising edge is valid. If CKE is Low. CKE controls power down and self-refresh. The power down and the self-refresh commands are entered when the CKE is driven Low and exited when it resumes to High. CKE must be maintained high throughout read or write access. The CKE level must be kept for 1 CK cycle at least, that is, if CKE changes at the cross point of the CK rising edge and the /CK falling edge with proper setup time tIS, by the next CK rising edge CKE level must be kept with proper hold time tIH. UDM, LDM (input pin) DMs are the reference signals of the data input mask function. DMs are sampled at the cross point of DQS and VREF. DMs provide the byte mask function. In x 16 products, LDM controls the lower byte (DQ0 to DQ7) and UDM controls the upper byte (DQ8 to DQ15) of write data. When DM = High, the data input at the same timing are masked while the internal burst counter will be count up. LDM controls the lower byte (DQ0 to DQ7) and UDM controls the upper byte (DQ8 to DQ15) of write data. DQ0 to DQ15 (input/output pins) Data is input to and output from these pins.
EO
Data Sheet E0749E10 (Ver. 1.0)
UDQS, LDQS (input and output pin): DQS provide the read data strobes (as output) and the write data strobes (as input). In x16 products, LDQS is the lower byte (DQ0 to DQ7) data strobe signal, UDQS is the upper byte (DQ8 to DQ15) data strobe signal. VDD, VSS, VDDQ, VSSQ (Power supply) VDD and VSS are power supply pins for internal circuits. VDDQ and VSSQ are power supply pins for the output buffers.
L
Pr od t uc
13
EDD2516AMTA-6B-E
Command Operation
Command Truth Table DDR SDRAM recognize the following commands specified by the /CS, /RAS, /CAS, /WE and address pins. All other combinations than those in the table below are illegal.
CKE Command Ignore command No operation Burst stop in read command Column address and read command Read with auto-precharge Symbol DESL NOP BST READ READA WRIT WRITA ACT PRE PALL REF SELF MRS n-1 H H H H H H H H H H H H H H n H H H H H H H H H H H L H H /CS H L L L L L L L L L L L L L /RAS /CAS /WE x H H H H H H L L L L L L L x H H L L L L H H H L L L L x H L H H L L H L L H H L L BA1 x x x V V V V V V x x x L L BA0 x x x V V V V V V x x x L H AP x x x L H L H V L H x x L L Address x x x V V V V V x x x x V V
EO
Write with auto-precharge Precharge select bank Precharge all bank Refresh Mode register set
Data Sheet E0749E10 (Ver. 1.0)
Column address and write command
Row address strobe and bank active
Remark: H: VIH. L: VIL. x: VIH or VIL V: Valid address input Note: The CKE level must be kept for 1 CK cycle at least. Ignore command [DESL] When /CS is High at the cross point of the CK rising edge and the VREF level, every input are neglected and internal status is held. No operation [NOP] As long as this command is input at the cross point of the CK rising edge and the VREF level, address and data input are neglected and internal status is held. Burst stop in read operation [BST] This command stops a burst read operation, which is not applicable for a burst write operation. Column address strobe and read command [READ] This command starts a read operation. The start address of the burst read is determined by the column address (See "Address Pins Table" in Pin Function) and the bank select address. After the completion of the read operation, the output buffer becomes High-Z. Read with auto-precharge [READA] This command starts a read operation. After completion of the read operation, precharge is automatically executed.
Column address strobe and write command [WRIT] This command starts a write operation. The start address of the burst write is determined by the column address (See "Address Pins Table" in Pin Function) and the bank select address. Write with auto-precharge [WRITA] This command starts a write operation. After completion of the write operation, precharge is automatically executed.
L
EMRS
Pr
14
od
t uc
EDD2516AMTA-6B-E
Row address strobe and bank activate [ACT] This command activates the bank that is selected by BA0, BA1 and determines the row address (AX0 to AX12). (See Bank Select Signal Table) Precharge selected bank [PRE] This command starts precharge operation for the bank selected by BA0, BA1. (See Bank Select Signal Table) [Bank Select Signal Table]
BA0 Bank 0 Bank 1 Bank 2 Bank 3 L H L H BA1 L L H H
EO
CKE Truth Table
Current state Idle Idle Idle Self refresh Power down
Data Sheet E0749E10 (Ver. 1.0)
Remark: H: VIH. L: VIL. Precharge all banks [PALL] This command starts a precharge operation for all banks. Refresh [REF/SELF] This command starts a refresh operation. There are two types of refresh operation, one is auto-refresh, and another is self-refresh. For details, refer to the CKE truth table section. Mode register set/Extended mode register set [MRS/EMRS] The DDR SDRAM has the two mode registers, the mode register and the extended mode register, to defines how it works. The both mode registers are set through the address pins (the A0 to the A12, BA0 to BA1) in the mode register set cycle. For details, refer to "Mode register and extended mode register set".
Remark: H: VIH. L: VIL. x: VIH or VIL. Notes: 1. All the banks must be in IDLE before executing this command. 2. The CKE level must be kept for 1 CK cycle at least.
L
Command Self-refresh entry (SELF) Self refresh exit (SELFX) Power down exit (PDEX)
Auto-refresh command (REF)
Power down entry (PDEN)
Pr
CKE n-1 n /CS H H L H L L H L L H L L H H L L H H L L L H H H
/RAS L L H x x x
/CAS L L H x x x
/WE H H H x x x
Address x x x x x x x x
Notes 2 2
od
H H H H
H
H
t uc
15
EDD2516AMTA-6B-E
Function Truth Table The following tables show the operations that are performed when each command is issued in each state of the DDR SDRAM.
Current state Precharging*1 /CS H L L L L L L L
2
/RAS /CAS /WE x H H H H L L L x x H H L L H H L x H H L L H H x H L H L H L x x H L H L H L
Address x x x BA, CA, A10 BA, CA, A10 BA, RA BA, A10 x x x x BA, CA, A10 BA, CA, A10 BA, RA BA, A10 x MODE x x x x
Command DESL NOP BST READ/READA WRIT/WRITA ACT PRE, PALL
Operation NOP NOP ILLEGAL*
11
Next state ldle ldle -- -- -- -- ldle -- ldle ldle
11 11
ILLEGAL*11 ILLEGAL*
11 11
ILLEGAL* NOP ILLEGAL
EO
Idle* H L L L L L L L L Refresh (auto-refresh)*3 H L L L L Activating*4 H L L L L L L L Active*
5
DESL NOP BST READ/READA WRIT/WRITA ACT PRE, PALL REF, SELF MRS DESL NOP BST
NOP NOP ILLEGAL* ILLEGAL*
H H H H
-- -- -- Active ldle ldle/ Self refresh ldle ldle ldle -- -- -- Active Active
ILLEGAL*11 Activating NOP Refresh/ Self refresh*12 Mode register set*12 NOP NOP ILLEGAL ILLEGAL ILLEGAL NOP NOP ILLEGAL*
11
L L
Data Sheet E0749E10 (Ver. 1.0)
L
L L H L L L x x x H H H L x H H H H L L L x H H H H L L L H H L x H L x x x x H H L H L H L x x H L H L H L x H L L H H L x H H L L H H L H L L L L L L L
Pr
x x DESL NOP BST x x BA, CA, A10 READ/READA WRIT/WRITA ACT BA, CA, A10 BA, RA BA, A10 x x x x BA, CA, A10 BA, CA, A10 BA, RA BA, A10 x PRE, PALL DESL NOP BST READ/READA WRIT/WRITA ACT PRE, PALL
od
ILLEGAL*11 ILLEGAL*
11 11
-- -- -- -- -- -- Active
ILLEGAL*
ILLEGAL*11
ILLEGAL
NOP
t uc
NOP Active ILLEGAL Active Starting read operation Read/READA Write Starting write operation recovering/ precharging -- Idle ILLEGAL*11 Pre-charge ILLEGAL --
16
EDD2516AMTA-6B-E
Current state Read*
6
/CS H L L L L L L L
/RAS /CAS /WE x H H H H L L L x x H H L L H H L x H H L L H H L x H L H L H L x x H L H L H L x
Address x x x BA, CA, A10 BA, CA, A10 BA, RA BA, A10 x x x x BA, CA, A10 BA, CA, A10 BA, RA BA, A10 x x x x
Command DESL NOP BST READ/READA WRIT/WRITA ACT PRE, PALL
Operation NOP NOP BST Interrupting burst read operation to start new read ILLEGAL*13 ILLEGAL*
11
Next state Active Active Active Active -- -- Precharging -- Precharging Precharging -- -- -- -- -- -- Write recovering Write recovering -- Read/ReadA
14
Interrupting burst read operation to start pre-charge ILLEGAL
EO
Read with auto-preH charge*7 L L L L L L L Write*
8
DESL NOP BST READ/READA WRIT/WRITA ACT PRE, PALL
NOP NOP ILLEGAL ILLEGAL*14 ILLEGAL* ILLEGAL*11, 14 ILLEGAL*11, 14 ILLEGAL
H H H H
L L L x
Write recovering*
9
Data Sheet E0749E10 (Ver. 1.0)
L
H x x L H H H L L L H H H L H L L L L H L L L L L L L H L L L x H H H H L L L L L H H L x x H L H L H L x H L x H H L L H H L
DESL NOP BST
NOP NOP ILLEGAL Interrupting burst write operation to start read operation. Interrupting burst write operation to start new write operation. ILLEGAL*11 Interrupting write operation to start precharge.
Pr
BA, CA, A10 BA, CA, A10 BA, RA ACT BA, A10 x x x x PRE, PALL DESL NOP BST BA, CA, A10 BA, CA, A10 BA, RA BA, A10 x ACT PRE/PALL
READ/READA
WRIT/WRITA
Write/WriteA -- Idle -- Active Active --
od
ILLEGAL NOP NOP ILLEGAL READ/READA WRIT/WRITA ILLEGAL*
11 11
t uc
Starting read operation. Read/ReadA Write/WriteA -- -- Starting new write operation. ILLEGAL* ILLEGAL --
17
EDD2516AMTA-6B-E
Current state Write with autopre-charge*10
/CS H L L L L L L L
/RAS /CAS x H H H H L L L x H H L L H H L
/WE x H L H L H L x
Address x x x BA, CA, A10 BA, CA, A10 BA, RA BA, A10 x
Command DESL NOP BST READ/READA WRIT/WRIT A ACT PRE, PALL
Operation NOP NOP ILLEGAL ILLEGAL* ILLEGAL*
14 14
Next state Precharging Precharging -- -- -- -- -- --
ILLEGAL*11, 14 ILLEGAL*11, 14 ILLEGAL
Remark: Notes: 1. 2. 3. 4. 5. 6.
H: VIH. L: VIL. x: VIH or VIL The DDR SDRAM is in "Precharging" state for tRP after precharge command is issued. The DDR SDRAM reaches "IDLE" state tRP after precharge command is issued. The DDR SDRAM is in "Refresh" state for tRFC after auto-refresh command is issued. The DDR SDRAM is in "Activating" state for tRCD after ACT command is issued. The DDR SDRAM is in "Active" state after "Activating" is completed. The DDR SDRAM is in "READ" state until burst data have been output and DQ output circuits are turned off. 7. The DDR SDRAM is in "READ with auto-precharge" from READA command until burst data has been output and DQ output circuits are turned off. 8. The DDR SDRAM is in "WRITE" state from WRIT command to the last burst data are input. 9. The DDR SDRAM is in "Write recovering" for tWR after the last data are input. 10. The DDR SDRAM is in "Write with auto-precharge" until tWR after the last data has been input. 11. This command may be issued for other banks, depending on the state of the banks. 12. All banks must be in "IDLE". 13. Before executing a write command to stop the preceding burst read operation, BST command must be issued. 14. The DDR SDRAM supports the concurrent auto-precharge feature, a read with auto-precharge enabled,or a write with auto-precharge enabled, may be followed by any column command to other banks, as long as that command does not interrupt the read or write data transfer, and all other related limitations apply. (E.g. Conflict between READ data and WRITE data must be avoided.) The minimum delay from a read or write command with auto precharge enabled, to a command to a different bank, is summarized below.
EO
From command Read w/AP Write w/AP
Data Sheet E0749E10 (Ver. 1.0)
L
Read or Read w/AP Write or Write w/AP Read or Read w/AP Write or Write w/AP
To command (different bank, noninterrupting command)
Precharge or Activate
Precharge or Activate
Pr
BL/2 1 BL/2 1
od
Minimum delay (Concurrent AP supported) CL(rounded up)+ (BL/2) 1 + (BL/2) + tWTR
Units tCK tCK tCK tCK
t uc
tCK tCK
18
EDD2516AMTA-6B-E
Command Truth Table for CKE
Current State CKE n-1 n Self refresh H L L L L L Self refresh recovery H H H x H H H H L H H H H L L L L x H /CS x H L L L x H L L L H L L L x H L x /RAS /CAS /WE Address x x H H L x x H H L x H H L x x x x x x H L x x x H L x x H L x x x H x x x H L x x x x x x x x x x x x x x x x H x x x x x x x x Maintain power down mode Refer to operations in Function Truth Table Refer to operations in Function Truth Table Refer to operations in Function Truth Table CBR (auto) refresh x x x x x x x x x x x x x x Operation INVALID, CK (n-1) would exit self refresh Self refresh recovery Self refresh recovery ILLEGAL ILLEGAL Maintain self refresh Idle after tRC Idle after tRC ILLEGAL ILLEGAL ILLEGAL ILLEGAL ILLEGAL ILLEGAL INVALID, CK (n - 1) would exit power down EXIT power down Idle Notes
EO
H H H H H Power down H L L L All banks idle H H H H H H H H H H L Row active H L
Data Sheet E0749E10 (Ver. 1.0)
Remark: H: VIH. L: VIL. x: VIH or VIL Note: 1. Self refresh can be entered only from the all banks idle state. Power down can be entered only from all banks idle or row active state.
L
H L H H H L L H H H H L L L L L x x x H L L L L L H L x H L L L L x x x L L x x x
Pr
H L x x x L x x H L L x x x H L x x x x x x x
OPCODE Refer to operations in Function Truth Table Refer to operations in Function Truth Table Refer to operations in Function Truth Table
Refer to operations in Function Truth Table Self refresh 1
od
Power down Power down
OPCODE Refer to operations in Function Truth Table 1
Refer to operations in Function Truth Table 1
t uc
19
EDD2516AMTA-6B-E
Auto-refresh command [REF] This command executes auto-refresh. The banks and the ROW addresses to be refreshed are internally determined by the internal refresh controller. The average refresh cycle is 7.8 s. The output buffer becomes High-Z after autorefresh start. Precharge has been completed automatically after the auto-refresh. The ACT or MRS command can be issued tRFC after the last auto-refresh command. Self-refresh entry [SELF] This command starts self-refresh. The self-refresh operation continues as long as CKE is held Low. During the selfrefresh operation, all ROW addresses are repeated refreshing by the internal refresh controller. A self-refresh is terminated by a self-refresh exit command. Power down mode entry [PDEN] tPDEN (= 1 cycle) after the cycle when [PDEN] is issued. The DDR SDRAM enters into power-down mode. In power down mode, power consumption is suppressed by deactivating the input initial circuit. Power down mode continues while CKE is held Low. No internal refresh operation occurs during the power down mode. [PDEN] do not disable DLL. Self-refresh exit [SELFX] This command is executed to exit from self-refresh mode. To issue non-read commands, tSNR has to be satisfied. ((tSNR =)10 cycles for tCK = 7.5 ns or 12 cycles for tCK = 6.0 ns after [SELFX]) To issue read command, tSRD has to be satisfied to adjust DOUT timing by DLL. (200 cycles after [SELFX]) After the exit, input auto-refresh command within 7.8 s. Power down exit [PDEX] The DDR SDRAM can exit from power down mode tPDEX (1 cycle min.) after the cycle when [PDEX] is issued.
EO
Data Sheet E0749E10 (Ver. 1.0)
L
Pr od t uc
20
EDD2516AMTA-6B-E
Simplified State Diagram
SELF REFRESH SR ENTRY SR EXIT
MODE REGISTER SET
MRS IDLE
REFRESH
*1 AUTO REFRESH
CKE CKE_
EO
POWER APPLIED
ACTIVE POWER DOWN
ACTIVE CKE_ CKE ROW ACTIVE
IDLE POWER DOWN
BST READ
WRITE Write WRITE WITH AP WRITE READ READ WITH AP READ WITH AP
Read
READ
Note: 1. After the auto-refresh operation, precharge operation is performed automatically and enter the IDLE state.
Data Sheet E0749E10 (Ver. 1.0)
L
WRITE WITH AP WRITEA POWER ON
READ WITH AP
PRECHARGE READA PRECHARGE PRECHARGE
Automatic transition after completion of command. Transition resulting from command input.
Pr
PRECHARGE PRECHARGE
od
21
t uc
EDD2516AMTA-6B-E
Operation of the DDR SDRAM
Power-up Sequence The following sequence is recommended for Power-up. (1) Apply power and attempt to maintain CKE at an LVCMOS low state (all other inputs may be undefined). Apply VDD before or at the same time as VDDQ. Apply VDDQ before or at the same time as VTT and VREF. (2) Start clock and maintain stable condition for a minimum of 200 s. (3) After the minimum 200 s of stable power and clock (CK, /CK), apply NOP and take CKE high. (4) Issue precharge all command for the device. (5) Issue EMRS to enable DLL. (6) Issue a mode register set command (MRS) for "DLL reset" with bit A8 set to high (An additional 200 cycles of clock input is required to lock the DLL after every DLL reset). (7) Issue precharge all command for the device. (8) Issue 2 or more auto-refresh commands. (9) Issue a mode register set command to initialize device operation with bit A8 set to low in order to avoid resetting the DLL.
(4) (5) (6) (7) (8) (9)
EO
/CK CK
L
EMRS MRS 2 cycles (min.) DLL enable
Command
PALL
PALL tRP
REF REF tRFC
REF tRFC
MRS 2 cycles (min.)
Any command
2 cycles (min.) 2 cycles (min.) DLL reset with A8 = High
Disable DLL reset with A8 = Low 200 cycles (min)
Mode Register and Extended Mode Register Set
There are two mode registers, the mode register and the extended mode register so as to define the operating mode. Parameters are set to both through the A0 to the A12 and BA0, BA1 pins by the mode register set command [MRS] or the extended mode register set command [EMRS]. The mode register and the extended mode register are set by inputting signal via the A0 to the A12 and BA0, BA1 during mode register set cycles. BA0 and BA1 determine which one of the mode register or the extended mode register are set. Prior to a read or a write operation, the mode register must be set. Remind that no other parameters shown in the table bellow are allowed to input to the registers.
Pr
A8 DR A7 0 A6 A5 0 0 LMODE 1 1 0 2.5
Power-up Sequence after CKE Goes High
od
A4 A3 A2 BT A3 Burst Type 0 Sequential 1 Interleave 0 0 0 0 1 1
BA0 0
BA1 0
A12 0
A11 A10 A9 0
A1 BL
A0
t uc
A2 A1 A0 Burst Length BT=0 BT=1 2 2 1 4 4 0 1 8 8
MRS A8 DLL Reset A6 A5 A4 CAS Latency 2 010 0 No 1 Yes
Mode Register Set [MRS] (BA0 = 0, BA1 = 0)
Data Sheet E0749E10 (Ver. 1.0)
22
EDD2516AMTA-6B-E
BA0 BA1 1 0 A12 A11 A10 A9 0 0 0 0 A8 0 A7 0 A6 0 A5 0 A4 0 A3 0 A2 0 A1 DS A0 DLL
EMRS A1 Driver Strength 0 Normal 1 Weak A0 DLL Control 0 DLL Enable 1 DLL Disable
Extended Mode Register Set [EMRS] (BA0 = 1, BA1 = 0) Burst Operation The burst type (BT) and the first three bits of the column address determine the order of a data out.
Burst length = 2 A0 0 1 Sequence 0, 1, 1, 0, Interleave 0, 1, 1, 0, Burst length = 4 Starting Ad. Addressing(decimal) A1 0 0 1 1 Addressing(decimal) Interleave 0, 1, 2, 3, 4, 5, 6, 7, 1, 0, 3, 2, 5, 4, 7, 6, 2, 3, 0, 1, 6, 7, 4, 5, 3, 2, 1, 0, 7, 6, 5, 4, 0, 1, 2, 3, 4, 5, 6, 7, 1, 2, 3, 4, 5, 6, 7, 0, 2, 3, 4, 5, 6, 7, 0, 1, 3, 4, 5, 6, 7, 0, 1, 2, 4, 5, 6, 7, 0, 1, 2, 3, 5, 6, 7, 0, 1, 2, 3, 4, 7, 0, 1, 2, 3, 4, 5, 6, A0 0 1 0 1 Sequence 0, 1, 2, 3, 1, 2, 3, 0, 2, 3, 0, 1, 3, 0, 1, 2, Interleave 0, 1, 2, 3, 1, 0, 3, 2, 2, 3, 0, 1, 3, 2, 1, 0,
EO
A2 0 0 0 0 1 1 1 1 A1 0 0 1 1 0 0 1 1
Data Sheet E0749E10 (Ver. 1.0)
Starting Ad. Addressing(decimal)
Burst length = 8 Starting Ad.
L
0 1 0 1 0 1 0 1
A0 Sequence
Pr
6, 7, 0, 1, 2, 3, 4, 5,
4, 5, 6, 7, 0, 1, 2, 3, 5, 4, 7, 6, 1, 0, 3, 2, 6, 7, 4, 5, 2, 3, 0, 1, 7, 6, 5, 4, 3, 2, 1, 0,
od t uc
23
Timing Waveforms
Command and Addresses Input Timing Definition
CK /CK
Read Timing Definition
/CK CK
DQS
DQ (Dout)
Write Timing Definition
/CK CK
DQS
DQ (Din)
DM
Data Sheet E0749E10 (Ver. 1.0)
;;;;;;
EDD2516AMTA-6B-E
tIS tIH Command (/RAS, /CAS, /WE, /CS) VREF tIS tIH Address VREF
EO
tCK
tCH
tCL
tDQSCK
tDQSCK
tDQSCK
tDQSCK tRPST
tRPRE
tDQSQ
tLZ
tAC
tQH tAC
tDQSQ
tAC
tQH tHZ
L
tCK tDQSS tWPRES tWPRE tDS tDS
tQH
tDQSQ tQH
tDQSQ
Pr
tDSS tDQSL tDH tDH
tDSH
tDSS
VREF
tDQSH
tWPST
od
tDIPW tDIPW tDIPW
VREF
VREF
t uc
24
EDD2516AMTA-6B-E
Read Cycle
tCK tCH tCL CK /CK VIH CKE tRCD tIS tIH /CS tIS tIH /RAS tIS tIH tIS tIH tIS tIH tIS tIH tRAS tIS tIH tRP tIS tIH tRC
EO
tIS tIH /CAS tIS tIH /WE tIS tIH BA tIS tIH A10 tIS tIH Address DM DQS High-Z DQ (output) High-Z Bank 0 Active
Data Sheet E0749E10 (Ver. 1.0)
tIS tIH
tIS tIH
tIS tIH
tIS tIH
tIS tIH
tIS tIH
tIS tIH
tIS tIH
tIS tIH
tIS tIH
tIS tIH
tIS tIH
L
tIS tIH
tIS tIH
Pr
tRPRE Bank 0 Read
tRPST
od
Bank 0 Precharge
CL = 2 BL = 4 Bank0 Access = VIH or VIL
t uc
25
EDD2516AMTA-6B-E
Write Cycle
tCK tCH CK /CK VIH CKE tRCD tIS tIH /CS tIS tIH /RAS tIS tIH tIS tIH tIS tIH tIS tIH tIS tIH tRC tRAS tRP tIS tIH tCL
EO
tIS tIH /CAS tIS tIH /WE tIS tIH BA tIS tIH A10 tIS tIH Address DQS (input) DM DQ (input) Bank 0 Active
Data Sheet E0749E10 (Ver. 1.0)
tIS tIH
tIS tIH
tIS tIH
tIS tIH
tIS tIH
tIS tIH
tIS tIH
tIS tIH
tIS tIH
tIS tIH
tIS tIH
tIS tIH
L
tIS tIH tDQSS tDQSL tDQSH tWPST
tIS tIH
Pr
tDS tDS
tDH
tDS
tDH
od
tWR
tDH Bank 0 Write
Bank 0 Precharge
CL = 2 BL = 4 Bank0 Access = VIH or VIL
t uc
26
EDD2516AMTA-6B-E
Mode Register Set Cycle
0 /CK CK CKE /CS /RAS /CAS /WE VIH 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15
EO
BA Address DM valid DQS DQ (output)
code code R: b C: b
High-Z High-Z tRP tMRD Bank 3 Active Bank 3 Read Bank 3 Precharge CL = 2 BL = 4 = VIH or VIL b
Read/Write Cycle
/CK CK CKE /CS /RAS /CAS /WE BA Address DM DQS DQ (output) DQ (input) Bank 0 Active R:a 0 VIH 1
Data Sheet E0749E10 (Ver. 1.0)
L
Precharge If needed
2 3 C:a High-Z
Mode register set
Pr
4 5 6 7 8 R:b a tRWD Bank 0 Bank 3 Read Active
9
10
11
12
13
14
15
od
C:b b Bank 3 Write tWRD
C:b''
t uc
b'' Bank 3 Read Read cycle CL = 2 BL = 4 =VIH or VIL
27
Auto Refresh Cycle
/CK CK
CKE /CS
/RAS /CAS /WE BA
Address
DQS
DQ (output) DQ (input)
Data Sheet E0749E10 (Ver. 1.0)
;;;;;
EDD2516AMTA-6B-E
VIH A10=1 R: b C: b DM b High-Z
; ;; ;; ; ; ;;
EO L
tRP Precharge If needed tRFC Auto Refresh Bank 0 Active Bank 0 Read CL = 2 BL = 4 = VIH or VIL
;;;;; ;;; ; ;;; ; ;;; ;;;;; ;; ;;; ;
Pr
28
od
t uc
EDD2516AMTA-6B-E
Self Refresh Cycle
/CK CK CKE
tIS
tIH CKE = low
/CS /RAS
/CAS
/WE
EO
BA Address A10=1 DM
R: b
C: b
L
tRP Precharge If needed Self refresh entry
DQS DQ (output) DQ (input)
High-Z tSNR tSRD Bank 0 Active Bank 0 Read CL = 2.5 BL = 4 = VIH or VIL
Pr
Self refresh exit
od t uc
Data Sheet E0749E10 (Ver. 1.0)
29
EDD2516AMTA-6B-E
Package Drawing
66-pin Plastic TSOP (II) Solder plating: Lead free (Sn-Bi)
Unit: mm
22.22 0.10 *
A
1
66
34
PIN#1 ID
1
0.65
33
B 0.80 Nom 0 to 10
0.22 +0.1 *2 -0.05
0.13 M S A B
11.76 0.20
10.16
1.0 0.05
1.20 max
S
0.10 S
0.125 0.075
0.125 +0.05 -0.02
EO
0.71 0.86 max
Data Sheet E0749E10 (Ver. 1.0)
0.25
L
0.60 0.15
Pr
30
Notes: 1. This dimension does not include mold flash. 2. This dimension does not include trim offset.
ECA-TS2-0097-01
od t uc
EDD2516AMTA-6B-E
Recommended Soldering Conditions
Please consult with our sales offices for soldering conditions of the EDD2516AMTA. Type of Surface Mount Device EDD2516AMTA: 66-pin Plastic TSOP (II) < Lead free (Sn-Bi) >
EO
Data Sheet E0749E10 (Ver. 1.0)
L Pr od t uc
31
EDD2516AMTA-6B-E
NOTES FOR CMOS DEVICES
1 PRECAUTION AGAINST ESD FOR MOS DEVICES
Exposing the MOS devices to a strong electric field can cause destruction of the gate oxide and ultimately degrade the MOS devices operation. Steps must be taken to stop generation of static electricity as much as possible, and quickly dissipate it, when once it has occurred. Environmental control must be adequate. When it is dry, humidifier should be used. It is recommended to avoid using insulators that easily build static electricity. MOS devices must be stored and transported in an anti-static container, static shielding bag or conductive material. All test and measurement tools including work bench and floor should be grounded. The operator should be grounded using wrist strap. MOS devices must not be touched with bare hands. Similar precautions need to be taken for PW boards with semiconductor MOS devices on it.
HANDLING OF UNUSED INPUT PINS FOR CMOS DEVICES
EO
2 3
Data Sheet E0749E10 (Ver. 1.0)
No connection for CMOS devices input pins can be a cause of malfunction. If no connection is provided to the input pins, it is possible that an internal input level may be generated due to noise, etc., hence causing malfunction. CMOS devices behave differently than Bipolar or NMOS devices. Input levels of CMOS devices must be fixed high or low by using a pull-up or pull-down circuitry. Each unused pin should be connected to VDD or GND with a resistor, if it is considered to have a possibility of being an output pin. The unused pins must be handled in accordance with the related specifications.
STATUS BEFORE INITIALIZATION OF MOS DEVICES
Power-on does not necessarily define initial status of MOS devices. Production process of MOS does not define the initial operation status of the device. Immediately after the power source is turned ON, the MOS devices with reset function have not yet been initialized. Hence, power-on does not guarantee output pin levels, I/O settings or contents of registers. MOS devices are not initialized until the reset signal is received. Reset operation must be executed immediately after power-on for MOS devices having reset function.
L
Pr
32
CME0107
od t uc
EDD2516AMTA-6B-E
The information in this document is subject to change without notice. Before using this document, confirm that this is the latest version.
No part of this document may be copied or reproduced in any form or by any means without the prior written consent of Elpida Memory, Inc. Elpida Memory, Inc. does not assume any liability for infringement of any intellectual property rights (including but not limited to patents, copyrights, and circuit layout licenses) of Elpida Memory, Inc. or third parties by or arising from the use of the products or information listed in this document. No license, express, implied or otherwise, is granted under any patents, copyrights or other intellectual property rights of Elpida Memory, Inc. or others. Descriptions of circuits, software and other related information in this document are provided for illustrative purposes in semiconductor product operation and application examples. The incorporation of these circuits, software and information in the design of the customer's equipment shall be done under the full responsibility of the customer. Elpida Memory, Inc. assumes no responsibility for any losses incurred by customers or third parties arising from the use of these circuits, software and information. [Product applications] Elpida Memory, Inc. makes every attempt to ensure that its products are of high quality and reliability. However, users are instructed to contact Elpida Memory's sales office before using the product in aerospace, aeronautics, nuclear power, combustion control, transportation, traffic, safety equipment, medical equipment for life support, or other such application in which especially high quality and reliability is demanded or where its failure or malfunction may directly threaten human life or cause risk of bodily injury. [Product usage] Design your application so that the product is used within the ranges and conditions guaranteed by Elpida Memory, Inc., including the maximum ratings, operating supply voltage range, heat radiation characteristics, installation conditions and other related characteristics. Elpida Memory, Inc. bears no responsibility for failure or damage when the product is used beyond the guaranteed ranges and conditions. Even within the guaranteed ranges and conditions, consider normally foreseeable failure rates or failure modes in semiconductor devices and employ systemic measures such as fail-safes, so that the equipment incorporating Elpida Memory, Inc. products does not cause bodily injury, fire or other consequential damage due to the operation of the Elpida Memory, Inc. product. [Usage environment] This product is not designed to be resistant to electromagnetic waves or radiation. This product must be used in a non-condensing environment. If you export the products or technology described in this document that are controlled by the Foreign Exchange and Foreign Trade Law of Japan, you must follow the necessary procedures in accordance with the relevant laws and regulations of Japan. Also, if you export products/technology controlled by U.S. export control regulations, or another country's export control laws or regulations, you must follow the necessary procedures in accordance with such laws or regulations. If these products/technology are sold, leased, or transferred to a third party, or a third party is granted license to use these products, that third party must be made aware that they are responsible for compliance with the relevant laws and regulations.
EO
Data Sheet E0749E10 (Ver. 1.0)
L
Pr
33
M01E0107
od t uc

▲Up To Search▲

Price & Availability of EDD2516AMTA-6B-E

	To Download EDD2516AMTA-6B-E Datasheet File
If you can't view the Datasheet, Please click here to try to view without PDF Reader .